The inventions relate to semiconductor integrated circuit devices (for example, memory devices); and more particularly, in one aspect, to circuitry and techniques to write and read, sense and/or sample a data state to/from memory cells of a memory array and/or device, for example, a semiconductor dynamic random access memory (“DRAM”) device, wherein the memory cells have an electrically floating body in which an electrical charge is stored.
There is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials and devices that improve performance, reduce leakage current and enhance overall scaling. Silicon-on-Insulator (SOI) is a material in which such devices may be fabricated on or in (hereinafter collectively “on”). Such devices are known as SOI devices and include, for example, partially depleted (PD), fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET. SOI devices have demonstrated improved performance (for example, speed), reduced leakage current characteristics and considerable enhancement in scaling.
One type of DRAM memory cell is based on, among other things, a floating body effect of SOI transistors. (See, for example, U.S. patent application Ser. No. 10/450,238, Fazan et al., filed Jun. 10, 2003 and entitled “Semiconductor Device”, hereinafter “Semiconductor Memory Device Patent Application”). In this regard, the memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) having a gate dielectric, which is disposed adjacent to the body and separated therefrom by a channel. The body region of the transistor is electrically floating in view of the insulation or non-conductive region (for example, in bulk-type material/substrate) disposed beneath the body region. The state of the memory cell is determined by the concentration of charge within the body region of the SOI transistor.
With reference to FIGS. 1A, 1B and 1C, in one embodiment, semiconductor memory cell array 10 includes a plurality of memory cells 12 each consisting of transistor 14 having gate 16, body region 18, which is electrically floating, source region 20 and drain region 22. The body region 18 is disposed between source region 20 and drain region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in SOI material/substrate) or non-conductive region (for example, in bulk-type material/substrate). The insulation or non-conductive region may be disposed on or in substrate 26.
Data is written into or read from a selected memory cell by applying suitable control signals to selected word line(s) 28, selected source line(s) 30 and/or selected bit line(s) 32. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18. Notably, the entire contents of the Semiconductor Memory Device Patent Application, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
As mentioned above, memory cell 12 of array 10 operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) 34 from body region 18 of, for example, an N-channel transistor. (See, FIGS. 2A and 2B). In this regard, accumulating majority carriers (in this example, “holes”) 34 in body region 18 of memory cells 12 via, for example, impact ionization near source region 20 and/or drain region 22, is representative of a logic high or “1” data state. (See, FIG. 2A). Emitting or ejecting majority carriers 34 from body region 18 via, for example, forward biasing the source/body junction and/or the drain/body junction, is representative of a logic low or “0” data state. (See, FIG. 2B).
Notably, for at least the purposes of this discussion, a logic high or State “1” corresponds to an increased concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with a logic low or State “0”. In contrast, a logic low or State “0” corresponds to a reduced concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with a logic high or State “1”.
As mentioned above, conventional techniques to write or program a logic low (State “0”) in memory cell 12 may be accomplished by removing majority carriers from body region 18 through either source region 20 or drain region 22 of electrically floating body transistor 14 of memory cell 12. In this regard, in one embodiment, majority carriers (in this example, “holes”) 34 in body region 18 of memory cells 12 are removed from memory cell 12 through drain region 22. (See, FIG. 3A). A positive current 36 (electrons flowing in opposite direction) flows from drain region 22 to source region 20 due to a channel forming in a portion of body region 18 immediately beneath gate oxide 38 when writing or programming a logic low (State “0”). Where the majority carriers (in this example, “holes”) 34 are removed from memory cell 12 through source region 20, positive current 36 (electrons flowing in opposite direction) flows from source region 20 to drain region 22 as a result of channel formation when writing or programming a logic low (State “0”). (See, FIG. 3B).
Conventional techniques may employ a two-cycle write or program technique to store a desired data state in memory cells 12. In this regard, in one embodiment, in the first cycle a logic low (State “0”) is written into all memory cells 12 connected to word line 28; in the second cycle, a logic high (State “1”) is selectively written into memory cells 12 while an inhibit signal or voltage is applied to those memory cells 12 that are to maintain a logic low or State “0”. In this way, certain memory cells 12 connected to a given word line may be written or programmed to a logic low (State “0”) using a first word line voltage; and certain other memory cells 12, also connected to the given word line, may be written or programmed to a logic high (State “1”) using a second word line voltage. (See, for example, application Ser. No. 10/840,009, which was filed by Ferrant et al. on May 6, 2004, and entitled “Semiconductor Memory Device and Method of Operating Same”).
Several techniques may be implemented to read the data stored in the memory cell. For example, a current sense amplifier may be employed to read the data stored in memory cells. In this regard, a current sense amplifier may compare the cell current to a reference current, for example, the current of a reference cell. From that comparison, it may be determined whether the memory cell contained a logic high data state (relatively more majority carriers contained within body region) or logic low data state (relatively less majority carriers contained within body region). The differences of the charge stored in the body of the transistor affect the threshold voltage of the transistor, which in turn affects the current conducted by the transistor when switched into its conductive state.
In particular, with reference to FIG. 4, sense amplifier 40 (for example, a cross-coupled sense amplifier) compares the current conducted by transistor 14 of memory cell 12 with a reference current generated by reference current generator 42. The magnitude of the reference current generally lies between the magnitudes of the currents conducted in the logic high data state and logic low data state of memory cell 12. The sense amplifier 40 compares the reference current to the current produced by memory cell 12 (the current varies depending on whether memory cell 12 is either in a logic high data state or logic low data state). Based on that comparison, sense amplifier 40 generates or outputs an output signal (on output 44) having a positive or negative polarity, depending upon whether memory cell 12 stored a logic high or logic low binary data state. (See, for example, U.S. Pat. No. 6,567,330; and “Memory Design Using a One-Transistor Cell on SOI”, IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, Nov. 2002).
The data sense circuitry/architecture and technique of the prior art have a number of shortcomings. For example, the data sense circuitry/architecture and technique of the prior art typically employ multiplexer circuitry to selectively apply one or more bit lines to the input of a sense amplifier bank. (See, for example, U.S. Pat. No. 6,567,330 and U.S. Pat. No. 6,650,565). Such circuitry/architectures often implement a pitch that differs from the pitch of the memory cell array. The bit line selection circuitry often adds complexity and latency to the read as well as write back operations. In addition, the bit line selection circuitry may introduce unwanted capacitance and inductance which may reduce the margin of the read operation. Finally, incorporation of bit line selection circuitry into the architecture typically eliminates the possibility of reading or writing an entire row of data.
There is a need for a data sense architecture and technique that eliminate the shortcomings of the prior art architectures and technique. For example, there is a need for an architecture and technique that is suitably and properly pitched to the array of memory cells. In this way, an entire row of data may be read, sampled and/or sensed without the complexity and latency of data sense architectures and techniques that implement bit line selection circuitry.